Finite element modelling of SAW correlator

Copyright 2007 Society of Photo-Optical Instrumentation Engineers. This paper was published in BioMEMS and Nanotechnology III, edited by Dan V. Nicolau, Derek Abbott, Kourosh Kalantar-Zadeh, Tiziana Di Matteo, Sergey M. Bezrukov, Proc. of SPIE Vol. 6799, 679915 and is made available as an electronic reprint with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.Numerical simulations of SAW correlators so far are limited to delta function and equivalent circuit models. These models are not accurate as they do not replicate the actual behaviour of the device. Manufacturing a correlator to specifically realise a different configuration is both expensive and time consuming. With the continuous improvement in computing capacity, switching to finite element modelling would be more appropriate. In this paper a novel way of modelling a SAW correlator using finite element analysis is presented. This modelling approach allows the consideration of different code implementation and device structures. This is demonstrated through simulation results for a 5×2-bit Barker sequence encoded SAW correlator. These results show the effect of both bulk and leaky modes on the device performance at various operating frequencies. Moreover, the ways in which the gain of the correlator can be optimised though variation of design parameters will also be outlined.Ajay C.Tikka Said F.Al-Sarawi and Derek Abbot

Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach

Copyright © 2004 IEEEThis paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gates based on systematic transistor level delay estimation using Logical Effort (LE). The adders are hybrid designs consisting of domino and the recently proposed Charge Recycling Threshold Logic (CRTL). The delay evaluation is based LE modeling of the delay of the domino and CRTL gates. From the initial estimations, we select the 8-bit sparse carry look-ahead/carry-select scheme. Simulations indicate a delay of less than 5 FO4, which is 1.1 FO4 or 17% faster than the nearest domino design.Peter Celinski, Said Al-Sarawi, Derek Abbott, Sorin Cotofana and Stamatis Vassiliadi

Fourth-order discrete-time variable centre frequency bandpass sigma-delta modulator

Copyright © 2006 IEEEA design for a variable centre frequency bandpass sigma-delta modulator is presented. The modulator is based on a tunable discrete-time resonator using only one control parameter. The noise transfer function of the modulator is controlled by a 4-bit digital signal, which provides nine different centre frequencies distributed between 0.1-0.4 normalized frequencies. The measurement results show a stable modulator at all centre frequenciesY. Zhu, S.F. Al-Sarawi, C. C. Lim, and M.J. Liebel

Hybrid parallel counters - Domino and threshold logic

Copyright © 2004 IEEEParallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi and Michael J. Liebel

Emerging physical unclonable functions with nanotechnology

Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs

Surface acoustic wave based wireless MEMS actuators for biomedical applications

Don W. Dissanayake, Said Al-Sarawi and Derek Abbot

High-sensitivity metamaterial-inspired sensor for microfluidic dielectric characterization

A new metamaterial-inspired microwave microfluidic sensor is proposed in this paper. The main part of the device is a microstrip coupled complementary split-ring resonator (CSRR). At resonance, a strong electric field will be established along the sides of CSRR producing a very sensitive area to a change in the nearby dielectric material. A micro-channel is positioned over this area for microfluidic sensing. The liquid sample flowing inside the channel modifies the resonance frequency and peak attenuation of the CSRR resonance. The dielectric properties of the liquid sample can be estimated by establishing an empirical relation between the resonance characteristics and the sample complex permittivity. The designed microfluidic sensor requires a very small amount of sample for testing since the cross-sectional area of the sensing channel is over five orders of magnitude smaller than the square of the wavelength. The proposed microfluidic sensing concept is compatible with lab-on-a-chip platforms owing to its compactness.Amir Ebrahimi, Withawat Withayachumnankul, Said Al-Sarawi and Derek Abbot

Memristive crypto primitive for building highly secure physical unclonable functions

Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of physical systems to generate secret information. The advantage is that PUFs have the potential to provide fundamentally higher security than traditional cryptographic methods by preventing the cloning of devices and the extraction of secret keys. Most PUF designs focus on exploiting process variations in Complementary Metal Oxide Semiconductor (CMOS) technology. In recent years, progress in nanoelectronic devices such as memristors has demonstrated the prevalence of process variations in scaling electronics down to the nano region. In this paper, we exploit the extremely large information density available in nanocrossbar architectures and the significant resistance variations of memristors to develop an on-chip memristive device based strong PUF (mrSPUF). Our novel architecture demonstrates desirable characteristics of PUFs, including uniqueness, reliability, and large number of challenge-response pairs (CRPs) and desirable characteristics of strong PUFs. More significantly, in contrast to most existing PUFs, our PUF can act as a reconfigurable PUF (rPUF) without additional hardware and is of benefit to applications needing revocation or update of secure key information.Yansong Gao, Damith C. Ranasinghe, Said F. Al-Sarawi, Omid Kavehei, Derek Abbot

Outcomes and uptake of explicit research skill development across degree programs

John Willison, Said Al Sarawi, Cynthia Bottema, Susan Hazel, Ursula Henderson, Sophie Karanicolas, Clinton Kempster, Ursula McGowan, Julia Miller, Kogi Naidoo, Brian Ng, Edward Palmer, Simon Pyke, Catherine Snelling, Richard Warner, Michael Wilmore, Glen Croy, Leanne McCann, Susan Mayson, Lyn Torres, Suniti Bandaranaike, Tai Peseta, Rowena Harpe